Phase lock loop (PLL) and other phase control circuits typically require a determination of when the circuit has achieved phase synchronization, i.e., "phase lock." It is generally desirable that this determination be made as accurately as possible in order to meet system performance requirements. In addition, a typical charge-pump type phase lock loop generates relatively large currents when in its acquisition mode, i.e., when it is seeking phase lock, and generates a relative smaller current when phase lock is achieved. Consequently, typical phase control systems attempt to quickly achieve phase lock and to maintain phase lock without oscillation in order to reduce power dissipation.
Towards this end, it is generally desirable in phase lock loops and other phase control circuits to accurately detect phase lock in a manner which is less susceptible to noise. It is also desirable to detect phase lock in a manner that is less prone to oscillation as the loop transitions in or out of phase lock.